# ECE 2700 Lab 2 solution

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## Description

Objectives
To learn how to build, simulate, and implement simple
combinational circuits in Verilog/Xilinx.
1 Pre-Lab Preparation
1. Construct truth tables for the circuits in Problem 2.52 from the main textbook.
2. Write Boolean equations for the digital system described in Problem 2.21 from the main textbook.
Draw the corresponding circuits.
Recall that you will not get the pre-lab credit if the prep work is not finished prior to your
assigned lab time.
Note that it may be useful to bring Lab 1 instructions, Taylor’s Verilog tutorial, and the secondary
text to lab for reference. Pay close attention to Chapter 6, which is a Verilog mini-reference. Also, the
example on page 34 shows how to use the built-in logic gates in Verilog.
2 Overview
In this lab, you will implement some simple combinational digital systems in Verilog, simulate your
designs, and implement one of the systems on the Basys board.
3 Part I
You will use simulations to determine if the two circuits in Problem 2.52 are equivalent. Create a new
directory called Lab2 inside the ECE2700 directory you created last week. Start Xilinx ISE and create a
new project called CircuitsComparison with 3 new files: circuit1.v, circuit2.v, and testbench.v.
Make sure that you specify the files as Verilog files.
Implement the circuit on the left-hand side in circuit1.v and the circuit on the right-hand side in
circuit2.v using built-in gates. Inside testbench.v, put in all possible test cases. Hint: there are 16
possible combinations.
Check for syntax errors and simulate your circuits. Verify the outputs and show the results to your TA.
Are the circuits equivalent?
4 Part II
In the second part of the lab, you will implement the digital system described in Problem 2.21 and load
it on the Basys board.
1
Create a new project titled disco system. You will want to create two new files to add to this project:
ds system.v, which will contain your Verilog code and disco test.v, which will contain your test cases.
Inside the file ds system.v, write out the Verilog code to implement the disco system described in
Problem 2.21 using built-in logic gates. Once you are done, write out all the possible test cases to
disco test.v. Each test vector should be simulated for 10 ns.
Check for any syntax errors and simulate your system. Show your results to the TA.
Create a UCF file. Locate SW0 and SW1 on the Basys board. SW0 and SW1 will correspond to the inputs
S (sound sensor) and M (motion sensor), respectively. LD0 and LD1 will correspond to the outputs L
(light) and B (ball), respectively. Perform appropriate pin assignments in the UCF file and take the steps