# ECE 2700 Lab 3 solution

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## Description

Objective
To become proficient in designing more complex combinational circuits in Verilog.
1 Preparation
1. Read this document in its entirety.
2. Draw a circuit showing how you might build a 4⇥1 mux from 2⇥1 muxes.
3. Read Example 2.23 in the main textbook on pages 72–73 and prepare the truth table for a 4-bit
binary number to hexadecimal 7-segment display. That is, in addition to 0-9, the display also
shows A, b, C, d, E, and F.
4. Read the 2-page reference manual (attached to the end of this document) to better understand the
seven-segment display connections.
2 Multiplexer Design
2.1 Building a 4⇥1 Mux
Inside your ECE2700 directory, create a new folder called Lab3. Start up Xilinx and create a new project
called MuxExp inside the Lab3 directory.
Create a new file called mux4x1.v. Inside, design a 4⇥1 mux using the provided 2⇥1 mux (mux2x1.v on
Canvas).
Be sure to declare your 4⇥1 mux as follows: module mux4x1(I3, I2, I1, I0, S1, S0, D), where I3,
I2, I1, and I0 are data inputs, S1 and S0 are control inputs, and D is the output. Make sure to design
your mux such that when S0 = 0, S1 = 0, D = I0, and when S0 = 1, S1 = 1, D = I3.
Test your design using the bench file mux4test.v from Canvas. Show your results to the TA.
2.2 Using the Muxes
Create a new file called shifter.v. You are to design a simple shifter using the 4⇥1 mux(es) you
designed in earlier. The shifter has four 1-bit data inputs (i3, i2, i1, i0), two 1-bit control inputs
(s1, s0), and four 1-bit data outputs (d3, d2, d1, d0). The following table describes the desired behaviors
of the shifter. Be sure to declare your shifter as follows: module shifter(i3, i2, i1, i0, s1, s0,
d3, d2, d1, d0). Observe that i3 is the leftmost bit in the input.
s1 s0 Behavior Description Example
0 0 Hold Output is the same as input. Input: 1010, Output: 1010
0 1 Shift left Output is the input shifted left by one bit. Input: 0101, Output: 1010
The least significant bit is shifted in with a 0. Input: 1111, Output: 1110
1 0 Shift right Output is the input shifted right by one bit. Input: 0101, Output: 0010
The most significant bit is shifted in with a 0. Input: 1111, Output: 0111
1 1 Rotate Right Output is the input rotated right by one bit. Input: 1011, Output: 1101
1
Hint: Remember that a mux is simply a circuit that selects the output from one of the inputs. Think
about what the data and control inputs need to be for the shifter to work correctly.
Test your design using the bench file testshifter.v from Canvas. Show your results to the TA.
3 Decoder Design
3.1 Simple 7-Segment Display
For this part of the lab you will write code for the 7-segment display and load it onto the Basys board.
Create a new project called SevenSeg. Add a new source file seg7.v and write out your binary number
to hexadecimal 7-segment display using the following declaration: seg7(w, x, y, z, a, b, c, d, e,
f, g), where w, x, y, and z are the 4-bit binary input and a, b, c, d, e, f, and g are the outputs. (If you
are unsure what to do, remember that you have prepared a truth table. From the truth table, you can
convert to Boolean equations and write them directly in Verilog.) Run simulations to make sure your
design is correct.
Locate SW0, SW1, SW2, and SW3 on the Basys board. These switches will represent the 4-bit binary number
input. As mentioned earlier, the output (corresponding hex value) will be displayed on the 7-segment
display. From reading the reference manual and looking inside MainBasys.ucf, you will see that although
the 7-segment display contains 4 digits, there are only 7 pin assignments for the 7-segment LEDs, not
28.