## Description

1. Consider the fundamental discrete time control system block given in the Figure below. Let

+

− r(t) G

c

(z) G

p ZOH (s)

δ

T

y*(t)

δ

T

r*(t)

δ

T

y(t)

GP (s) = 1

s

2 + 1

, T1 = 0.1s , T2 = 0.5s

Then

(a) For each sampling-time value (T1 = 0.1s and T2 = 0.5s), design two different digital Phase-Lead

compensators such that

• closed-loop system is stable (for all cases),

• steady state error to the unit step response is less than %10 (for all cases),

• and phase-margin requirements for the compensated systems (for both sampling times) are

– φm,1 ∈ [10o

, 150

],

– φm,2 ∈ [25o

, 300

].

After the design of compensators provide the (discrete-time) bode plots of all cases and label the

phase margin values on the bode plots.

(b) Using MATLAB or Simulink, plot the step responses of all four closed-loop systems and compare

the results in terms of steady-state error, over-shoot, and settling-time.

∗This document c M. Mert Ankarali

1