Description
ECE:3350 Project Part 1
In this first part of the project you will implement the modules and datapath depicted below:
You are given:
• All of alu.v, rf.v, statreg.v, mux4.v, and mux32.v, which you may not modify.
• Detailed descriptions of each module’s function and control lines, in block comment form, at
the top of every Verilog file provided to you.
• A mostly empty ctrl.v, which contains descriptions for the inputs and outputs, as well as some
parameters, reset processes, and other miscellaneous data.
• A mostly empty sisc.v, which contains descriptions for the inputs and outputs.
You are required to:
• Finish the implementation of ctrl.v as a finite state machine, so that the control lines shown
above in orange operate correctly as described by the given files. Note that you are only to
implement the control for the R type instructions and the ADD immediate instruction.
• Finish the implementation of sisc.v which contains a module ‘sisc’ that instantiates each of the
six modules shown above, and connects their control and data signals.
• You are given a Verilog file named ‘sisc_tb_p1.v’ which contains a module ‘sisc_tb’ that
instantiates the sisc module, drives the CLK and RST_F signals as described below, and
generates instructions that test each of the supported instructions for Part 1.
• Scan or digitally draw a state diagram for the FSM in ctrl.v and save it in your project folder.
• Compress your project directory, including the ‘work’ directory and the state diagram, into a
.zip file named ‘project_p1.zip’ and submit it to your “Verilog Project – Part 1” dropbox on
ICON.
Part 1 Notes:
• Download the sisc_p1_files.zip file from Canvas and unzip the files to a sisc_p1_files
directory.
• Read the documentation included with each file carefully before beginning to connect them.
• In the RF module, the outputs of the register file R[A] and R[B] are latched in the RSA and
RSB registers on the positive edge of the clock.
• In the ALU module, the output of the ALU is latched in the ALUOut register on the positive
edge of the clock.
• The sisc module should take in three inputs (IR, CLK, and RST_F) and have no outputs.
• The sisc_tb module should have no inputs or outputs.
• In the testbench file, the clock process runs at the rate of 1 cycle/10 time units. Since the
default time unit in ModelSim is 1 ns, this gives us a 10 ns clock period. The RST_F reset line
is active low and is held at 0 for 20 ns or 2 clock cycles before being set to logic 1. Generation
of the first instruction is delayed until time = 35 ns so that it appears at IR on the second clock
cycle after the reset line has been set to logic 1. All further instructions are delayed by 50 ns
per instruction to allow all five cycles to execute in the control unit. At the time the instruction
changes, the cntrl.v module should enter the DECODE state.
• The instructions your design should support by the end of Part 1 are NOP, ADD, ADD IMM,
SUB, NOT, OR, AND, XOR, ROTR, ROTL, SHFR, SHFL, and HLT. Always include a HLT
command at the end of your instructions to end execution.
• You may use any $monitor(…) statements you wish to test your design, but in the sisc.v file
that you submit, please monitor the following signals: IR, R1 through R6, RD_SEL, ALU_OP,
WB_SEL, RF_WE, and the 32-bit line connected to the write_data input of the rf module.
o To monitor a signal within an instantiated module, such as R1 and R2, use the dot
operator. If you have instantiated module rf with the name my_rf, you can access R1
with the following syntax: $monitor(“R1=%h”, my_rf.ram_array[1]);.
Submission Overview:
• Your .zip file should be named “Project_p1.zip” and contain:
o A short description of your project implementation and the names of your project team.
o Alu.v, mux4.v, mux32.v, rf.v, and statreg.v, exactly as they were provided.
o Ctrl.v, sisc.v, and sisc_tb_p1.v, completed by your group.
▪ Note that sisc.v should contain the $monitor statement described above!
o The ‘work’ directory.
o Your FSM state diagram.
o Your simulation transcript.
o ModelSim screen captures.
Part 1 Grading Rubric:
FSM Diagram 10 pts
Ctrl.v Implementation 15 pts
Sisc_tb.v Implementation 15 pts
Correct Execution of All Instructions 30 pts
Total 70 pts
ECE:3350 Project Part 2
For this part of the project, you are to include in the datapath the modules for program counter
control, instruction memory, and branch execution, as shown below.
You are given:
• Your own solution from Part 1. We will not provide a working solution to build off of, so it is
imperative that you finish Part 1 before moving on to Part 2.
• An imem.data file that contains all of the instructions from Part 1. You are provided this so that
you may be certain that your modifications from Part 1 to Part 2 have not broken the original
functionality. (See the note about imem.data below for more information.)
• The Verilog files pc.v, br.v, ir.v, and im.v (with descriptions provided), which you are not to
modify.
You are required to:
• Modify the sisc module to instantiate and connect the pc, br, ir, and im modules.
• Modify the control unit to generate the new RD_SEL, BR_SEL, PC_RST, PC_WRITE,
PC_SEL, and IR_LOAD signals, while not disrupting the control signals from Part 1.
• In the ctrl.v module, implement instruction fetch, and the branch instructions.
• Update the FSM state machine you created for Part 1 to reflect your new ctrl.v.
• Compress your project folder and submit it to the “Verilog Project – Part 2” ICON dropbox.
Part 2 Notes:
• You are given a new testbench file that only generates the clock and reset signals.
• About imem.data: When the simulation of your design begins, the im module reads the data
in the file imem.data and stores it. The data is written in 32-bit hexadecimal strings (8
hexadecimal digits each), sequentially from address 00 onward. In-line comments can be
included if they are preceded by two forward slash characters (//Just like in C). You may want
to keep the original contents of imem.data as a reference of how to format the instructions. The
imem.data file also contains new instructions to test that the branch instructions work correctly.
• You will no longer have to control the timing of the instructions with delays. If your control
unit correctly generates the program counter and branch signals, the instructions will be read
during the instruction fetch stage by the im module.
• Be careful when implementing the PC update and branch control signals! The PC must be
incremented as part of the Fetch state. This ensures that the PC has the correct value at the end
of instruction execution for all instructions that do not modify the PC. In addition, this ensures
that the incremented value of the PC is available to the BR module at the beginning of the
Decode state. For the branch instructions where the branch is taken, the PC is again updated
in the Decode state with the new PC value originating in the BR module
• Again, you may use any $monitor(…) statements you wish to test your design, but your
submitted sisc.v should monitor the following signals: IR, PC, R1 through R5, ALU_OP,
BR_SEL, PC_WRITE, and PC_SEL.
• After simulation, save your transcript file!
Submission Overview:
• Your .zip file should be named “Project_p2.zip” and contain the following:
o A description of your part 2 design and the names of your project partners.
o Alu.v, br.v, im.v, mux4.v, mux32.v, pc.v, ir.v, rf.v, and statreg.v, exactly as they
were provided.
o Ctrl.v, and sisc.v completed by your group.
▪ Again, sisc.v should contain the $monitor statement described above.
o The ‘work’ directory.
o The transcript information from your simulation.
o ModelSim screen captures.
o Your updated FSM state diagram.
Grading Rubric:
Revised FSM Diagram 10 pts
Correct Execution of Pt. 1 Instructions 15 pts
Correct Execution of Pt. 2 Instructions 30 pts
Ctrl.v Implementation 15 pts
Total 70 pts
ECE:3350 Project Part 3
This part has two distinct goals: 1) Complete the datapath by adding the data memory and
modifying the control unit to support load and store instructions (as shown below), and 2) Modify
the datapath to support the SWAP instruction, and write two machine-language programs to test
your design. More details are given below.
You are given:
• Your own solution to Part 2. Again, you will not be able to succeed in Part 3 without first
completing Part 2.
• An imem.data file containing a program designed to test all of the instructions from Parts 1 and
2 and the LDX, LDA, STX and STA instructions of part 3. This is so that you can be sure your
modifications for Part 3 have not broken your previous functionality.
• Three example data memory files (datamemory.data, sort_data.data and mult_data.data).
• The Verilog files dm.v and mux16.v (complete with descriptions), which you are not to modify.
• The diagram shown above.
You are required to:
• Modify the ctrl and sisc modules to include the new control lines and modules for the load and
store instructions. Note that your sisc_tb file should not need to change from Part 2.
• Simulate your design using the supplied imem.data file and verify that the load and store
instructions are working
Now modify the datapath to support the SWP instruction:
• Follow these guidelines while making your changes to the datapath:
o You may create any new control lines or modules you deem necessary.
o You may not remove or modify any provided file except the multiplexers.
o Update the imem.data file to test the SWP instruction.
o Your final solution must still correctly execute all of the previous instructions.
• Update the FSM state diagram and datapath diagram to reflect your modifications, for both the
load and store instructions and the swap instruction.
• Write two machine language programs:
o Sort a list of N signed, 32-bit integers stored in main memory using the bubble sort
algorithm. This program must use your newly implemented SWAP instruction at least
once. The number of integers in the list, N, will be stored in memory location 0, with the
integers stored at addresses 1 through N. After execution of your program, the integers
should be in ascending order (least integer stored at address 1, and greatest stored at address
N). An example list is provided in sort_data.data. Save this instruction memory file as
sort_instr.data.
o Multiply two unsigned, 32-bit integers stored in memory and write the resulting 64 bit
product back to memory. The two integers will be stored in memory locations 0 and 1, and
the product should be written to locations 2 and 3, such that the most significant bits are at
address 2. An example data file is provided as mult_data.data. Save this instruction
memory file as mult_instr.data.
• Compress your project folder, along with the ‘work’ directory, the three instruction memory
files, the data memory files, updated state diagram, and all .v files into a .zip file named
“Part3.zip”.
Details/Notes:
• Part 3 contains two significant tasks: the addition of load and store instructions, and the
modifications to implement SWAP. I highly suggest that, once you finish the changes
necessary to support load and store instructions, you copy your project folder somewhere
safe, so that even if you don’t complete the SWAP implementation, you will be guaranteed to
get the points for the load and store section. Additionally, if you are stuck on the SWAP
modifications and need to restart them, you can begin from the saved copy and won’t need to
re-implement load and store as well.
• Note that for the SWP instruction, you are required to write two values back to the register file
in one instruction execution cycle. This is possible if you write one value during the mem
cycle and one during the writeback cycle.
Submission Overview:
• Your .zip file should be named “Part3.zip” and contain the following:
o All the .v and .data files
o The ‘work’ directory.
o Your updated FSM state diagram.
o An updated datapath diagram.
Rubric:
FSM and Datapath Diagrams 10 pts
Load and Store Implementation 15 pts
Swap Implementation 15 pts
Bubble Sort 10 pts
Multiplication 10 pts
AllInstr.data 10 pts
Total 70 pts
ECE:3350 Project Part 4
This part of the project worth 66 points. You are to implement the LDP, LDR, STP, and STR
instructions. Note that the new instructions effectively allow for auto-increment and decrement
load and store instructions.
You are given:
• Your own solution to Part 3. Again, you will not be able to succeed in Part 4 without first
completing Part 3.
You are required to:
• Modify any of the project .v files as needed to implement the new instructions
• Write a testbench program in imem.data that tests every SISC-supported instruction and
addressing mode (I recommend modifying the one provided with part 3). Save this instruction
memory file as all_instr.data. If there is an associated data memory file this program uses,
save it as all_data.data.
• Follow these guidelines while making your changes to the datapath: You may create any new
control lines or modules you deem necessary.
o You may not remove any provided file but you may modify any file provided.
o Your final solution must still correctly execute all of the previous instructions.
• Update the FSM state diagram and datapath diagram to reflect your modifications needed for
the new instructions.
• Compress your project folder, along with the ‘work’ directory, the instruction memory files,
the data memory files, updated state diagram, and all .v files into a .zip file named
“Project_p4.zip”.
Details/Notes:
Like the SWAP instruction, the new LOAD instruction addressing modes will require
that two values be written to the register file during instruction execution. Be careful
with the timing!
Submission Overview:
• Your .zip file should be named “Project_p4.zip” and contain the following:
o All the .v and .data files
o The ‘work’ directory.
o Your updated FSM state diagram.
o An updated datapath diagram.
Rubric:
FSM and Datapath Diagrams 10 pts
Load and Store Implementation 40 pts
Instr.data 16 pts
Total 66 pts