ECE3270 Lab 1: Design of basic gates and I/O solution




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Lab Overview: The purpose of this exercise is to learn how to connect simple input and output devices to an FPGA
chip and implement a circuit that uses these devices. We will use the switches SW9-0 and push-buttons KEY3-0 on the
DE1-SoC board as inputs to the circuit. We will use light emitting diodes (LEDs) and 7-segment displays as output
devices. The requirements for this lab consist of completing the QUARTUS designs, demoing the designs, and
completing the laboratory report using the LaTeX template. For more information regarding pins and I/O for the
DE1-SoC board (in these and all labs), please refer to the user manual available online and on Canvas.
You will submit your report to Turnitin on Canvas and your code to the Assign Server as Assignment 1 by the due
Background: The DE1-series board provides 10 toggle switches, called SW9-0, that can be used as inputs to a
circuit, and 10 red lights, called LEDR9-0, that can be used to display output values. Since there are 10 switches and
lights, it is convenient to represent them as arrays (STD_LOGIC_VECTOR) in the VHDL code.
The DE1-series board has hardwired connections between its FPGA chip and the switches and lights. To use SW9-0
and LEDR9-0 it is necessary to include in your Quartus project the correct pin assignments, which are given in the
DE1-series User Manual. For example, on the DE1-SoC board, SW0 is connected to the FPGA pin AB12 and LEDR0
is connected to pin V16. A good way to make the required pin assignments is to import into the Quartus II software
the file called DE1.qsf for the DE1-SoC board, which is provided on Canvas. The procedure for making pin
assignments is described in the tutorial Quartus Introduction using VHDL Design, which is also available from Intel.
It is important to realize that the pin assignments in the .qsf file are useful only if the pin names given in the file are
exactly the same as the port names used in your VHDL entity. The file uses the names SW[0] : : : SW[9] and
LEDR[0] : : : LEDR[9] for the switches and lights (note that the Quartus II software uses [ ] square brackets for
array elements, while the VHDL syntax uses ( ) round brackets).
Part I: Generate a D flip-flop that latches the input value on the rising or falling edge of a clock pulse. Use KEY[0]
to send a pulse to the flip-flop, use SW[0] as the input, and send the output value to LEDR[0].
Part II: Figure 4a below shows a sum-of-products circuit that implements a 2-to-1 multiplexer with a select input s.
If s = 0 the multiplexer’s output m is equal to the input x, and if s = 1 the output is equal to y. Part b of the figure
gives a truth table for this multiplexer, and part c shows its circuit symbol.
The multiplexer can be described by the following Data Flow VHDL statement:
m <= (NOT (s) AND x) OR (s AND y);
1. Write a VHDL entity that describes the circuit given in Figure 5a (an eight-bit wide 2-to-1 multiplexer).
This circuit has two eight-bit inputs, X and Y, and produces the eight-bit output M. If s = 0 then M = X,
while if s = 1 then M = Y. It has the circuit symbol shown in Figure 5b, in which X, Y, and M are depicted
as eight-bit wires (vectors).
2. Simulate with a test bench.
3. Synthesize, Place & Route, download the bitstream for your design onto the DE1 board, and test the
Part III: Modify your design to create a circuit where the output m is selected from five 3-bit inputs u, v, w, x, and
1. Simulate with a test bench.
2. This part requires too many switches to test on the board, you can only verify with a testbench.
Part IV: Figure 8 shows a 7-segment decoder module that has the three-bit input c2c1c0. This decoder produces
seven outputs that are used to display a character on a 7-segment display. Table 1 below lists the characters that
should be displayed for each valuation of c2c1c0 (plus the ‘blank’ character, which is selected for codes 101 – 111).
The seven segments in the display are identified by the indices 0 to 6 shown in Figure 8. Each segment is
illuminated by driving it to the logic value 0.
1. Write a VHDL entity/architecture to activate each of the seven segments. Use only simple VHDL
assignment statements in your code to specify each logic function. Connect the outputs of the decoder to
the HEX0 display on the DE1-series board. The segments in this display are called HEX00, HEX01, : : :,
HEX06, corresponding to Figure 8. You should declare the 7-bit port:
2. Simulate with a test bench.
3. Synthesize, Place & Route, download the bitstream for your design onto the DE1 board and test the
Table 1.
c2c1c0 Character
000 H
001 E
010 L
011 O
Part V: Consider the circuit shown in Figure 9. It uses a three-bit wide 5-to-1 multiplexer (Part III) to enable the
selection of five characters that are displayed on a 7-segment display. Using the 7-segment decoder from Part IV this
circuit can display any of the characters H, E, L, O and ‘blank’. The character codes are set according to Table 1 by
using the switches SW2-0, are latched with KEY3-0, and a specific character is selected for display by setting the
switches SW9-7. Note Figure 9 only shows a portion of the design that displays a single character, you will need to
replicate everything past the D Flip-Flops for each character (with modifications).
1. Use circuits from Parts I, II and III as subcircuits in this code to drive five 7-segment displays rather than
just one. The purpose of your circuit is to display any word on the five displays that is composed of the
characters in Table 1, and be able to rotate this word in a circular fashion across the displays when the
switches SW9-7 are toggled. As an example, if the displayed word is “HELLO”, then your circuit should
produce the output patterns illustrated in Table 2.
2. Simulate with a test bench.
3. Synthesize, Place & Route, download the bitstream for your design onto the DE1 board, and test the
Table 2.
SW9SW8SW7 Character Pattern
000 H E L L O
001 O H E L L
010 L O H E L
011 L L O H E
100 E L L O H
– Proper format
– All sections included
– Valid images where applicable
– Proper grammar, punctuation, and spelling
– 10%
– 30%
– 5%
– 5%
– Live Demonstration
o Includes working code and answering questions from the
– Comments
o Thoughtful comments, not English translations of code
– 35%
– 5%
Proper Assign Server Code Submission 10%