Description
Purpose: In this project you are asked to define and test a Half Adder
Objectives:
- Continue to get familiar with EDAPlayground
- Continue to learn HDL (Verilog) basics
- To understand arithmetic logic unit: half and full adder
Step 1: Define and Test a Half Adder (Refer to lab 1)
The Half Adder is a digital building block with 2 inputs (A, B) and 2 outputs (S, Cout). The Half Adder logic must be modeled next. The circuit below shows the Half Adder logic circuit and the equivalent boolean equations:
|
S = A xor B
Cout = A and B |
Binary Operator Symbols in Verilog
| ~ | NOT |
| *, /, % | mult, div, mod |
| +, – | add,sub |
| <<, >> | shift |
| <<<, >>> | arithmetic shift |
| <, <=, >, >= | comparison |
| ==, != | equal, not equal |
| &, ~& | AND, NAND |
| ^, ~^ | XOR, XNOR |
| |, ~| | OR, NOR |
| ?: | ternary operator |
This completes the verilog module definition of the half adder. Next it must be tested to ensure it works correctly.
Step 2: Create a Half Adder Verilog Test Fixture. To test a module for correct functionality, a set of inputs will be provided to produce an expected set of outputs. A Verilog Testbench is used to test a Verilog source module.
Create the Half Adder test script. To test a module for correct functionality, a set of inputs will be provided to produce an expected set of outputs. For simple modules like the half adder a truth table is used to show the outputs that can be expected from a set of inputs.
The Cout output column shows that Cout equals 1 only when A equals 1 and B equals 1.
The S output column shows that S equals 1 when the value of A is not equal to the value of B.
Simulation results are shown as waveforms. Steps to view and interpret simulation results are outlined on the next page.
Part 2: Define and test a Full Adder
(Read Chapter 5 page 240 of the textbook for an explanation of the Full Adder.)
Step 1: The plan! A Full Adder will be created using hierarchical design. A Full Adder can be made by using two instances of the Half Adder and an OR gate as shown below.
| Cin |
| ha1 |
| FullAdder |
| ha1_C |
| ha0_S |
| ha0_C |
| ha0 |
| Cout |
| FA_S |
| FA_B |
| FA_A |
The circuit has been annotated with extra labels for easy translation into Verilog. Below is the Verilog module to model everything within the dotted box above.
Take note of how the labels in the diagram correlate to the labels in the Verilog module. There are two instances of the HalfAdder module created in Part 1 of this lab. The instances have instance labels ha0 for HalfAdder zero and ha1 for HalfAdder one. Variables in Verilog are referred to as signals. A Verilog convention known as named port mapping is used to connect inputs and outputs of the HalfAdder to signals within the FullAdder. The port signals from the HalfAdder are preceded with the dot operator and signals from the FullAdder go in the following parenthesis. Local signals that are not inputs or outputs within the FullAdder must be declared using the wire keyword. Finally the OR gate is represented by the assignment statement where the OR logic operation.
Use the given truth table on the left to make your test cases.
Correct output waveform is supposed to show all eighth test cases as below:
Lab Report: Submit a single PDF or WORD to beachboard with the following contents.
- Title Page
- CECS 225
- Lab 4
- Your Name
- Section 1: FullAdder Verilog module source code
- Section 2: FullAdder Verilog Test code
- Section 3: FullAdder Simulation Screenshot showing correct results (make sure the order of input/output variables match the truth table)