Description
Purpose: Become familiar with the Hazards in pipelining, introducing stalls to encounter Hazards, introducing forwarding technique to reduce stalls and improve performance
Points: 100
Reading/References: Chapter 4, Class Lecture / Lecture Notes
Assignment: You can duplicate and edit the given tables as needed.
- Given the MIPS five stage pipeline and the following instruction sets:
- What is the number of cycles required for executing the following programs in a pipelined processor, and not considering any dependencies/hazards. [5 pts]
- b) Identify all data hazards (RAW, WAR, WAW) for the given Instruction set. [5pts]
- c) If there is no forwarding or hazard detection, write the instructions (same order) and insert nop‘s to force the appropriate number of stalls which would be required. [10 pts]
- d) If the processor has forwarding, what would happen when the following instruction set is executed? [10 pts]
- e) Use the techniques as needed- Rearrange (change the order if needed), forward, and temporary register for the given instruction set to avoid hazards where possible. Insert nop‘s to force the appropriate number of stalls when a hazard cannot be avoided even with forwarding. You can use register $15 to hold temporary values in the modified code. [10 pts]
Q1 Instruction set # 1:
I1: add $4, $5, $2
I2: sw $4, 0($1)
I3: or $1, $2, $4
I4: lw $5, 8($1)
I5: sub $3, $5, $2
I6: andi $2, $5, 3
I7: add $8, $9, $2
- Given basic MIPS five stage pipeline, complete the tables with no-forwarding and forwarding, for the following instruction set: (Refer Ch4_PracticeSheet4_KEY) [40 pts, 10 pts each]
- Detect all the Data Hazards for the given instruction set (RAW, WAR, WAW).
- Assuming forwarding not allowed. Assume that branches execute in the EX-stage, draw the pipeline execution diagram for each set of code.
Note for part (b): If the condition is branch as taken, then the decision is made in EX-stage. So, you can fetch the next instruction in next clock cycle only. If the condition is branch as not taken, then the following instruction (PC+4) is fetched in the next clock cycle without any flush.
- Forwarding allowed and insert stalls if forwarding is not possible. Assuming branch decision logic is moved to decode stage. Assume forwarding is available within the same cycle if registers, else in the next cycle for the other units/stages.
Note for part (c): If the condition is branch as taken, then the decision is made in decode stage. So, you can fetch the next instruction in next clock cycle only. If the condition is branch as not taken, then the following instruction (PC+4) is fetched in the next clock cycle without any flush.
- What is speed-up you attain by allowing forwarding?
Q2 Instruction set #1:
L1: lw $1, 24($6)
beq $1, $3, L2 # not taken
add $1, $6, $4
L2: beq $1, $2, L1 # taken
sw $2, 12($4)
and $1, $1, $4
No forwarding, insert nops
| Instruction Set | Pipeline Cycle | ||||||||||||
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | |
Forwarding allowed- insert bubbles/stalls or nop(s) as needed
| Instruction Set | Pipeline Cycle | ||||||||||||
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | |
- Explain the techniques to handle data hazards. Also explain how each technique may reflect the performance. What is idle case and why we use forwarding in pipelining? [Hint: You can talk about stalls] [10 pts]
- What is Exe to Exe forwarding, Mem to Mem forwarding, and Mem to Exe forwarding? Does a R-format instruction can forward from Mem to Exe? Does a R-format instruction can forward from Mem to Mem? If so, give examples for both cases in one instruction set only. You can use the tables like in Question 1 and 2. [10 pts]