Solved CS219 Assignment 5 (Ch4) Spring 2026

Description

Purpose: Become familiar with the MIPS architecture instruction formats, control signals, Datapath elements.

Points: 110

Reading/References: Chapter 4, Class Lecture / Lecture Notes, Textbook

• What are the steps to be followed to execute an instruction? (Check lecture notes and Ch4_part1 PPT)                                                            [10 pts]
• Define the following:          [10 pts, 2.5 pts each]

1. Clock signal
2. Control signal
3. Data
4. How an edge-triggered methodology allows a state element to be read and written in the same clock cycle

• Define combinational elements and give few examples                                     [5 pts]
• Define sequential (storage) elements and give few examples                         [5 pts]
• Explain the Datapath elements from Fig. 4.17 given below. Include the diagrams of each Datapath element and explain what is the role of that element to execute the instructions from R, and I-formats? (Note: You can copy and paste the diagrams from the textbook/PPT as needed in this assignment. No need of hand drawing)                                    [15 pts]
• The following table shows the number of instructions for a program. [15 pts]

1. Assuming that arith instructions take 1 cycle, load and store 5 cycles, and branches 2 cycles, what is the execution time of the program in a 3 GHz processor?
2. Find the CPI for the program before reducing the load instructions by half.
3. If the number of load instructions can be reduced by one half, what is the execution time of the program in a 3 GHz processor?
4. Find the CPI for the program after reducing the load instructions by half.
5. What is the speedup if the number of load instructions are reduced by one half?

Note: Answer the above parts (a-e) for processor B

You can follow the example given below to answer Question 6:

(Processor A is solved in next page)

Note: Execution Time (ET) is also known as CPU Time

a)Processor A:

CPU Clock Cycles=  1000*1+100*5+800*5+150*2=  5800

ET=1000*1+100*5+800*5+150*2/(3*10⁹)=  5800/(3*10⁹)= 1933.33 ns

1. b) CPI = Execution Time*clock rate/No. of Instructions

CPI for Processor A = 1933.33 * 10 ^-9 * 3*10⁹/2050= 5800/2050= 2.83

(Considered 5799.99 as 5800 for Processor A)

1. c) Load by one-half instructions

Processor A:

CPU Clock Cycles=  1000*1+100*5+400*5+150*2=  3800

ET=1000*1+100*5+400*5+150*2/(3*10⁹)=  3800/(3*10⁹)= 1266.66 ns

1266. CPI for Processor A = 1266.66 * 10 ^-9 *3*10⁹/1650= 3800/1650= 2.30

(Considered 3799.98 as 3800 for Processor A)

1. Speed-up of Processor A before and after load instructions reduction=

1933.33 ns/1266.66 ns= 1.52

• Write the working principle (Interpretation) of the following instructions and update the control unit signal table given below – sub, beq, andi, lw, sw. Also, Write the above instructions in pseudo format, for example write “add” instruction as add rd, rs, rt instead of add $t0, $t1, $t2. Use fig 4.17 for this question.                                                    [50 pts, 10 pts each]