Description
Purpose: Become familiar with the MIPS Instruction Language and Design principles
Reading/References: Chapter 2 Points: 100
Answer the below questions. Responses must be submitted in hand writing/word document via
the class web site. You can also submit your work in “.pdf” format.
1) Convert pseudocode to MIPS: (using bne/beq conditions) [15 pts]
a) if ($s2 != $s3)
$s4 = $s4 + $s5;
b) if ($s1 == $s2)
$s3 = $s3 + $s3;
c) if ($t0 == $t1)
$t2 = $t2 + $t2;
$t2 = $t2 + $t3;
2) Give an example to load a 32-bit constant into a register using MIPS assembly code. [10 pts]
3) Provide MIPS instructions that: extracts a field for the constant values of bits 7-22 from register $t0
($t0=0x56781234) and places it in the lower order portion of register $t3 (zero filled otherwise). [15 pts]
Note: You can use other registers as needed, however update them accordingly in the register table.
$t0 is represented in binary: (Note: Do not change the value of $t0 throughout this question)
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
Step 1: Write the MIPS assembly instruction(s) to match the output as given below in $t3.
$t3
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0
Update the following register table in hexadecimal values. Update all the registers used for step1.
Register table
$t0=0x56781234 $t3=
Step 2: Write the MIPS assembly instruction(s) to match the output as given below in $t3. The bits are
highlighted to illustrate the changes that are made after step1.
$t3
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0
Update the following register table in hexadecimal values. Update all the registers used for step2.
$t0=0x56781234 $t3=
4) Explain how lw and sw instruction (I-format) works. Explain how the address is calculated in
lw and sw instructions. What is exactly stored in rs register for both lw and sw instructions? What
is the role of rt (for example read(source) or write (destination)) in the given instructions. Use the
instructions that are given below: [30 pts, 15 pts each]
Assume 0x00004020 is the base address, and is stored in $s1. The content in 0x00004020
is 32, the content in 0x00004024 is 15, the content in 0x00004028 is 63, and the content in
0x0000402C is 0 initially. You have to update the content in registers $s2, $s1, and the
content in memory addresses 0x00004020, 0x00004024, 0x00004028, and 0x0000402C
after the lw instruction and the sw instruction.
Note: Given instructions are sequential and so do not reset the values
I1:lw $s2, 4($s1)
I2:sw $s2, 8($s1)
I1: lw $s2, 4($s1)
Register Data/Content
$s1
$s2
After the explanation of lw instruction as above guidelines, answer the following:
lw copies the content from register $s2 to the address calculated by ALU. True/False.
Justify your answer why it is True or False?
I2: sw $s2, 8($s1)
Register Data/Content
$s1
$s2
Address Data/Content
0x00004020
0x00004024
0x00004028
0x0000402C
After the explanation of sw instruction as above guidelines, answer the following:
sw copies the content from register $s2 to the address calculated by ALU. True/False.
Justify your answer why it is True or False?
Example of how an add instruction work:
add rd, rs, rt // rs and rt are used as source1 and source2 respectively (read); rd is destination
//register (write)
add $t2, $t0, $t1
Address Data/Content
0x00004020
0x00004024
0x00004028
0x0000402C
Here $t0 and $t1 are used for read operation
$t2 is used for write operation.
The content of register[t0] is added with the content of [t1] and the result is stored in [t2]
For example if you have $t0=0x00000010; and $t1= 0x00000020;
then $t2= 0x00000030
5) Submit an assembly file with MIPS code containing a beq or bne instruction. Explain how the branch
offset can be obtained through QTSpim. Using the given table, convert your assembly language instruction
into hexadecimal. [10 pts]
[You should also submit the screenshot as given below; your code on left side and QtSpim window on the
right. Do not copy/paste my code. Please come up with your own logic.]
bne $t0, $t1, L1
offset = (L1 – Current address of branch instruction)/4 = (0x00400040-0x00400034)/4=
12/4=3
6) Submit an assembly file with MIPS code containing a jump instruction. Explain how the jump offset
can be obtained through QtSpim. Using the given table, convert your assembly language instruction into
hexadecimal. [10 pts]
[You should also submit the screenshot as above; your code on left side and QtSpim window on the right.
Do not copy/paste my code. Please come up with your own logic.]
Example for jump instruction
j Loop
Address to jump= low-order 26-bits from Label Table/4
Address from Label Table= 0x0040004C
26-bits address from above is 040004C
So, address to jump= 040004C/4 =0x 100013
J-format
Instruction j Loop
Opcode
(6-bits)
Immediate
(26-bits)
2 0x100013
0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1
0 8 1 0 0 0 1 3
7) Given the hex opcode Hex: 0x16320019, what is the equivalent MIPS instruction (include
register names)? Show field values. [10 pts]