Description
Run HSpice simulations to answer the following questions.
1. Please design an inverter with (�⁄�)& = 1.8 ��⁄0.2 ��.
a. Find and report the PMOS size such that the transition point happens at
�123 = 0.5 ∙ �66 when �78 is also 0.5 ∙ �66.
b. What is the ratio between PMOS and NMOS? Why?
c. Simulate and plot the DC voltage transfer curve of this inverter as �123
vs. �78.
d. Find the values of �9:, �;<, �9<, and �;: at points with slope of −1.
e. What are the noise margins ��: and ��< of your design?
f. Complete the layout (including DRC and LVS). Show figures of your layout
with DRC and LVS reports.
2. Please design a NAND3 gate with all 3 NMOS sizes of 5.4 ��⁄0.2 ��.
a. Connect all three inputs together and design the PMOS sizes such that
the transition point happens at �123 = 0.5 ∙ �66 when �78 is 0.5 ∙ �66,
the same as the inverter in Q1. All three PMOS sizes should be the same.
b. What is the ratio between PMOS and NMOS? How is it compared to the
answer to Q1b and why?
c. Simulate and plot the DC voltage transfer curve of this inverter as �123
vs. �78 (with all three inputs tied together).
d. Find the values of �9:, �;<, �9<, and �;: at points with slope of −1.
e. What are the noise margins ��: and ��< of this design? How are
they compared to those of the inverter in Q1? Explain reasons for the
difference.
3. Simulate the above NAND3 gate with �B1CD of 100 fF at the output. Consider
input signals that go between 0 V and VDD with both the rise and fall time of 100
ps. Furthermore, only one of the three inputs is switching at a time.
a. Simulate the contamination delays for both rising and falling output. For
both rising and falling cases, explain the input pattern that results in this
shortest delay.
b. Simulate the worst-case propagation delays for both rising and falling
output. For both rising and falling cases, explain the input patterns that
result in this worst-case propagation delay.
c. Repeat the above two questions across the following 5 corners. Show the
waveforms with proper markers and complete the following table.
d. Please also submit the sp netlist along with your report.
Process Temperature �FDG �FDH �IDG �IDH
TT 25°C
FF –40°C
SS 125°C
SF 25°C
FS 25°C