Description
Problem 1: Circuit loading, filtering
R1
Vs
R2
Vo
C1
C2
Rs
RL
Design the bandpass RC filter to achieve >20dB attenuation at 1MHz and less than 0.1dB attenuation
from 1 Hz to 10 kHz.
a) First, ignoring loading effects, determine 3dB frequencies (f3dB,HP and f3db,LP) that meet the
specifications.
b) With Rs = 100Ω and RL = 10MΩ, choose R1, R2, C1, and C2 to minimize loading effects.
c) Simulate the frequency response (Vo/Vs) in Ltspice and plot it together with the ideal response
in MATLAB/Python.
Problem 2: Current sources, frequency response, loading
Is
Rout ZL
IL
Cout Vout
Use the circuit and variables (no values) for the following.
a) Sketch the frequency response (magnitude and phase) Vout/Is for ZL → .
b) Sketch the frequency response (magnitude and phase) Vout/Is together with the unloaded
response (part a) for the two conditions
1. ZL = CL
2. ZL = RL
c) Sketch the transient response of Vout for Is as a current step from 0 to Imax (ZL → ).
Problem 3: Sampling, settling, power dissipation
Tclk
clk
1
0
R
Vin C Vcap
The clock waveform shown above is used to drive the switch open and closed (clk = 1 → switch closed,
clk = 0 → switch open). Tclk is the clock period (50% duty cycle), where Tclk = 1/fclk. Vin = 1V, R = 100 Ω,
and C = 10 pF
a) What is the maximum clock frequency, fclk, that allows 0.1% settling precision of Vcap each
period?
b) Given this clock frequency, what is the average current delivered to the capacitor?
c) Verify your answers to a) and b) using Ltspice. To do this using a DC source fo Vin, you need to
use an initial condition (0V) on Vcap. Include any relevant plots in your submission.
d) Perform an AC simulation on the circuit in Ltspice (switch closed). Relate the frequency response
to the settling time and include any relevant plots.