Description
Introduction .
In this lab you will learn the basics of digital simulation using the ModelSim
simulation program as well as the use of the Timequest Timing Analyzer.
1. Design of a ARCCOS Circuit
For the course project you will need a circuit that will take in an unsigned 8-bit value, X,
and provide a 10-bit unsigned output, ANGLE, which represents 10*(arccosine(X)), in
units of 10th of a degree.
To do this, you will use an approximation, based on the Taylor’s Series expansion:
We need to convert this to a form where the input X is scaled to range from 0-255 (8
bits) and the output is scaled to be in 10th of a degree. Doing this we get an expression
that we can implement using unsigned integer operations:
(you should try to derive this formula yourself…)
The approximation is very poor as X approaches 256 but is better for lower values.
If we take X=128 and truncate the results of all operations to integer values, the above
formula gives 601, which is close to the exact value of 600.
cos−1(𝑥𝑥) ~ 𝜋𝜋
2 − 𝑥𝑥 − 𝑥𝑥3
6 − 𝑥𝑥5
40 ; in radians, for 𝑥𝑥 ∈ (0,1)
cos−1(𝑋𝑋) ~ 900 − 𝑋𝑋
29 1144 +
𝑋𝑋2
216 191 + 86
𝑋𝑋2
216
You should break the computation into a series of steps:
1. X2 = X*X
2. P1 = [86 * X2]/2^16
3. S1 = 191+P1
4. P2 = [S1*X2]/2^16
5. S2 = 1144+P2
6. P3 = [S2*X]/2^9
7. ANGLE = 900-P3
Perform the division by powers of 2 with right shifts, which can
be done easily just by discarding the appropriate number of LSBs.
Implement these operations in a single clocked process block.
—
— entity name: gNN_ARCCOS (replace “NN” by your group’s number)
—
— Version 1.0
— Authors: (list the group member names here)
— Date: March ??, 2023 (enter the date of the latest edit to the file)
library ieee; — allows use of the std_logic_vector type
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; — needed since you are using unsigned numbers
entity gNN_ARCCOS is
port ( X : in std_logic_vector(7 downto 0);
CLOCK : in std_logic;
ANGLE : out std_logic_vector(9 downto 0);
end gNN_ARCCOS;
VHDL Description of the ARCCOS circuit.
Using the following form for the entity declaration (replace the values in the header with
your own information), write the complete VHDL entity description for a circuit that
implements the ARCCOS operation.
Name this file gNN_ARCCOS.vhd, where NN is your group number.
In this course, we will be using the Modelsim simulation software, created by the
company Mentor Graphics (we will use a version of it specific to Quartus, called
Modelsim-Altera).
The Modelsim software operates on a Hardware Description Language (HDL)
description of the circuit to be simulated, written either in VHDL, Verilog, or
System-Verilog. You will use VHDL.
Run the Quartus program and create a new project called gNN_ARCCOS (where
“NN” is your group number). As in lab #0 set the device to Cyclone V
5CSEMA5F31C6
In Quartus, add your VHDL file to this new project and run “Processing/Start/Start
Analysis and Elaboration” on the VHDL file (we don’t need to do the
synthesis/fitting steps for now) and correct any errors you might have.
Simulation of the ARCCOS circuit using ModelSim
Next, double-click on the ModelSim desktop icon to startup the ModelSim
program. A window somewhat like the one shown below will appear.
7
Select FILE/New/Project and, in the window that pops up, give the project the
name “gNN_ARCCOS”
Click OK.
Another dialog box will appear, allowing you to add files to the project. Click
on “Add Existing File” and select the VHDL file that was generated earlier
(gNN_ARCCOS.vhd). You can also add files later.
(note that the various entries in the popup windows will be different for your
lab – these are just example images from previous years)
8
The ModelSim window will now show this vhdl file in the Project pane.
In order to simulate the design, ModelSim must analyze the VHDL files, a
process known as compilation.
The compiled files are stored in a library. By default, this is named “work”. You
can see this library in the “library” pane of the ModelSim window.
The question marks in the Status column in the Project tab indicate that either
the files haven’t been compiled into the project or the source file has changed
since the last compilation. To compile the files, select Compile > Compile All
or right click in the Project window and select Compile > Compile All.
If the compilation is successful, the question marks in the Status column will
turn to check marks, and a success message will appear in the Transcript pane.
The compiled vhdl files will now appear in the library “work”.
In the library window, double-click on gNN_ARCCOS. This will open a bunch of
windows which will be used in doing the simulation of the circuit.
You are not quite ready to start the simulation yet!
Notice that, in the “Objects” window, the signals all have the value “UUUUUU”. This
means that all of the inputs are undefined. If you ran the simulation now, the outputs would
also be undefined.
So, you need to have a means of setting the inputs to certain patterns, and of observing the
outputs’ responses to these inputs.
In Modelsim, this is done by using a special VHDL entity called a Testbench.
A testbench is some VHDL code that generates different inputs that will be applied to your
circuit so that you can automate the simulation of your circuit and see how its outputs
respond to different inputs.
It is important to realize that the testbench is only used in Modelsim for the
purposes of simulating your circuit. You will NOT synthesize the testbench into
real hardware.
Because of its special purpose (and that it will not be synthesized), the testbench
entity is unique in that it has NO inputs or outputs and uses some special
statements that are only used in test benches. These special statements are not
used when describing circuits that you will later synthesize to a FPGA.
The testbench contains a single component instantiation statement that inserts
the module to be tested (in this case the gNN_ARCCOS module), as well as
some statements that describe how the test inputs are generated.
After you gain more experience, you will be able to write VHDL testbenches from scratch.
However, Quartus has a convenient built-in process, called the Test Bench Writer, which
produces a VHDL template from your design that will get you started.
Go back to the Quartus program, making sure that you have the
gNN_ARCCOS project loaded.
Then, in the Processing toolbar item, select Start/Start Test Bench
Template Writer
This will generate a VHDL file named gNN_ARCCOS.vht and place it in the
simulation/modelsim directory. Open it up in Quartus. It will look something like this:
Note that the template already includes the instantiation of the
gNN_ARCCOS component.
It also includes the skeletons of two “process” blocks, one labeled “init” and
the other labeled “always”.
The init process block can be left blank for this lab but is usually used to
specify initial signal values and other initial conditions for the simulation.
You should edit the “always” process block to suit your needs, so in this case
it will be used to generate the input signal waveforms.
As a first test, enter the following code into the testbench file:
This just creates 3 different test patterns, each presented at different times.
signal clock : std_logic := ‘0’; — make sure you initialise the clock signal to get it started
— delete the init process block
always : PROCESS
— optional sensitivity list
— ( )
— variable declarations
BEGIN
— code executes for every event on sensitivity list
X <= x“10″; — value is 0.5 (128/256) (exact 10arccos is 600)
WAIT FOR 100 ns;
X <= x”00″; — value is 0 (exact 10arccos is 900)
WAIT FOR 100 ns;
X <= x“B5″; — value is 0.707 (181/256) (exact 10arccos is 450)
WAIT;
END PROCESS always;
Clock : PROCESS
BEGIN
clock <= not clock after 5 ns;
END PROCESS clock;
Once you have finished editing the testbench file, you need to add it to the
project in ModelSim (make sure you are in the “Project” pane):
Once the testbench file has been added to the project, you should select the
testbench file in the Project pane and click on Compile Selected from the
Compile toolbar item. This will compile the testbench file.
Now everything is ready for you to actually run a simulation!
Select “Start Simulation” from the Simulate toolbar item in the ModelSim program.
The following window will popup:
Select the gNN_ARCCOS_tst
entity and click on OK
The ModelSim window should now look like this. Enter a value of 500ns into
the simulation length window.
At first, the “Wave” window will not have any signals in it. You can drag signals from
the “Objects” window by clicking on a signal, holding down the mouse button, and
dragging the signal over to the Wave window. Do this for all the signals.
The Wave window will now look like this:
Now, to actually
run the
simulation, click
on the “Run”
icon in the
toolbar (or press
the F9 key).
Since we are working with wide multi-bit vector signals, it is inconvenient to view their
values as binary vectors. Instead, set the “Runtime Options” from the Simulate menu
and set the “Default Radix” to Hexadecimal.
Here is the output you should get (you can right-click in the right-hand pane
and select “Zoom Full” to see the entire time range).
To see the individual bits in a vector, click on the “+” next to the signal name
in the left-hand column. There are a lot of bits so usually you wouldn’t want to
do this unless you are trying to locate a glitch.
How many clock cycles are needed to arrive at the final result?
If you get an incorrect output waveform, you will have to go back and look at
your design. If you make a correction to either of your schematic diagrams, you
will have to re-run the conversion to VHDL (using the File/Create/Update/Create
HDL Design File from Current File… command).
Then you will have to re-run the compilation of the changed files in ModelSim.
Finally, to rerun the simulation, first click on the “Restart” button, then click on
the “Run” button.
Further Testing of the Project using ModelSim
The simulation you ran in the previous part of the lab just had a couple of input signal
transitions and did not test all possible input patterns.
There are 2^8=256 possible input patterns, which is small enough that complete testing
of the circuit is feasible.
Modify the testbench file to add a FOR loop that will generate the 256 test patterns, with
a WAIT of 8 nsec per loop (so a total of 2 microseconds for the simulation).
Rerun the simulation with this amended testbench. Capture of screenshot of the resulting
wave display for your report. Make sure that hexadecimal values are shown for the
signal vector values.
Compute the expected values of the arccos approximation and the exact values using a
calculator (or a computer program, such as in Matlab or python) for the 256 test values
and compare to the simulated outputs.
Although you do not have to do so for this lab, think about how you would check the
output values in VHDL using ASSERT statements.
To ensure a properly working circuit, the designer must take into
consideration various timing constraints. In class we saw that for a register
to correctly store an input value, the input must be held stable for a period
(called the setup time) before the clock edge, and also for a period (called
the hold time) after the clock edge.
Whether a circuit meets these timing constraints can only be known after
the circuit is synthesized. After synthesis is done one can analyze the
circuit to see if the timing constraints (setup and hold times) are satisfied.
In Quartus II, timing analysis can be done using the TimeQuest Timing
Analyzer.
Using the TimeQuest Timing Analyzer .
From the “File/New” menu item, select
“Synopsys Design Constraints File”.
This “.sdc” file is where we can specify
various timing constraints for our design.
We will add a single constraint specifying
the clock period.
The Quartus Fitter (the process that maps
the design to the FPGA logic array) will
attempt to do the mapping so as to meet the
constraints.
The gNN_ARCCOS.sdc file will be used to tell the timing analyzer
that your clock period is 4ns (corresponding to a clock frequency of
250MHz).
Enter the following single line into the file:
create_clock –period 4 [get_ports {clk}]
The Timing Analyzer will read the .sdc file and use the constraint
information when doing its analysis.
To tell the TimeQuest Timing Analyzer to use your constraints file, go to the
“Settings” item under the “Assignments” menu item. Add the file
“gNN_ARCCOS.sdc”. Also, select “Report worst-case paths during compilation”.
Compile your gNN_ARCCOS project.
After compiling your design, there will be a “TimeQuest Timing Analyzer”
section in the Compilation Report. Click on “Slow 1100mV 85C Model”.
Note that some of the headings will be in RED indicating a failed timing.
The Fmax reported in the Slow 1100mV 85C Model is less than that
specified in the constraints file.
Click on the “Setup Summary” report. This will list the minimum setup time slack value
over all paths in the circuit. The End Point TNS is the total negative slack summed over
all paths and can give you an idea of how extensive the timing problems are.
If this value is negative, then your circuit has timing problems somewhere.
Click on the “Timing Closure Recommendations” report. This will list the paths with
the most negative failing setup time slack values.
Make a note of which registers form the path. This will tell you where the maximum
delays are, usually due to long chains of logic such as adders/multipliers etc.
Try to determine where in your circuit the long delays are.
Click on the “Hold Summary” report for the Fast 100mV 0C. This will list the minimum
hold time slack value over all paths in the circuit. The End Point TNS is the total
negative slack summed over all paths and can give you an idea of how extensive the
timing problems are.
If this value is negative, then your circuit has timing problems somewhere. Usually, the
Hold time slacks are positive, but you should check them anyway.
Mark down the following values, which you should include in your report:
Requested Fmax = ___250 MHz_________________________
Fast 1100mV 0C Model Hold Slack Value =____________________
Slow 1100mV 85C Model Setup Slack Value = _________________
Slow 1100mV 85C Model Fmax =___________________________
List the Worst-case Timing paths for the Setup times.
It may be that with a 250MHz clock frequency request, the timing
analysis does not pass. In this case we have to lower the requested
clock frequency.
To try and get a passing timing analysis tell the timing analyzer that
your clock period is 8ns (corresponding to a clock frequency of
125MHz). Enter the following single line into the file:
create_clock –period 8 [get_ports {clk}]
The Timing Analyzer will read the .sdc file and use the constraint
information when doing its analysis.
Recompile the project and look at the new timing analysis report.
Does your circuit now pass the timing analysis?
If not, keep increasing the clock period in 1 nsec increments until the
timing analysis is passed.
Mark down the following values, which you should include in your report,
for the case where the timing analysis is passed with no problems:
Requested Fmax = ___?? MHz_________________________
Fast 1100mV 0C Model Hold Slack Value =____________________
Slow 1100mV 85C Model Setup Slack Value = _________________
Slow 1100mV 85C Model Fmax =___________________________
You should also take a look at the “Flow Summary” after the compilation.
In particular, take note of the usage of ALMs (adaptive logic modules). So far, you
should only be using a small fraction of the FPGA’s logic elements.
Also look at the Chip Planner, found in the Fitter report. It gives an overview of how
the design was mapped to the FPGA logic array.
Writeup the Lab Report .
Write up a short report describing the gNN_ARCCOS circuit that you designed in
this lab. This report should be submitted in pdf format.
The report must include the following items:
• A header listing the group number, the names and student numbers of each group
member, and a title, giving the name (e.g. gNN_ARCCOS) of the circuit.
• A description of the circuit’s function, listing the inputs and outputs.
• The VHDL description of the circuit.
• The final version of the VHDL testbench file.
• A screenshot of the simulation results for the first simulation run. This should
show clearly the hexadecimal values of the signals over the time interval 0 to 500
nsec. Compare the obtained results with pre-computed values (using a calculator).
• The contents of the timing constraints file (.sdc file).
• Timing analysis reports produced during the second part of the lab, including the
recorded values from pages 39 and 41.
Submit the Lab Report to myCourses .
The lab report, and all associated design files (the design files are the vhdl,
testbench and timing constraints (.vhd, .vht, .sdc) files) must be submitted, as an
assignment to the myCourses site. Only one submission need be made per group
(both students will receive the same grade).
Combine all of the files that you are submitting into one zip file and name the
zip file gNN_LAB_1.zip (where NN is your group number).